In a multiplexed bus system, many devices are connected to a common bus. If 2 or more devices attempt to use the bus at the same time , then data will be lost. Thus only one one device must be allowed to use the bus at a time. to rectify this we will connect the devices through tri-state devices , when disabled it will effectively discoonect devices from the bus.

binary counter with the number of bits available.
initiallly counter is set to zero. then bits are checked against logic 1 or 0,if they are either logic 1 or 0,then
counter is incremented.

Charging a Capacitor: The voltage across the capacitor is not instantaneously equal to that of the
voltage across the battery when the switch is closed. The voltage on the capacitor
builds up as more and more charges flows onto the capacitor until the battery is
no longer able to "push" any more charge onto the capacitor, at which point the
capacitor becomes fully charged.The initial flow of charges from the battery to
the capacitor means that there is a current flowing through the system until the
capacitor is charged. This current flow decays exponentially from some initial
value to zero.
DisCharging a Capacitor: Switch remains open and voltage across capaciotr decreses untill it reaches zero.

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Write Through. After writing in cache memory, main memory is updated too
inmediatly to mantain reliability.
Write Back After writing in cache memory a flag bit called dirty bit is set.
When this value need to be replaced that bit is check, if it is set then the
value is taken to main memory.

NAND gate is normally prefered because the mobility of holes in NAND gate is three times greater than mobility of electron.

In series of Inverter is placed, the charge sharing happen between the input capacitance with the help of an load capacitane but we cant get the desired logical output.

LVs means LAyout versus schematic -method to check the correctness of ur layout designed by cross checking with netlist generated from schematic using the tool.
DRC means Design Rules Checker - a tool for verifying the layout with the Physical layout design rules set so as to make sure that none of the rules have been violated.

clock skew is the time difference between the arrival of active clock edge to different flipflops of the same chip.

threshold voltage is defined as the minimum voltage that required to make the transistor ON. transistor may be either NMOS or PMOS.For NMOS the value of threshold voltage is positive value and for PMOS the value of threshold voltage is negative value.